Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias.
Domagoj SiprakMarc TieboutNicola ZanollaPeter BaumgartnerClaudio FiegnaPublished in: IEEE J. Solid State Circuits (2009)
Keyphrases
- noise reduction
- cmos technology
- low power
- analog vlsi
- low voltage
- signal to noise ratio
- delay insensitive
- power dissipation
- edge preserving
- power consumption
- circuit design
- median filter
- high speed
- vlsi circuits
- noise removal
- noise level
- edge detection
- mixed signal
- low cost
- noisy environments
- edge enhancement
- noise filtering
- noise free
- image sensor
- wiener filter
- random access memory
- asynchronous circuits
- chip design
- nm technology
- multiscale
- edge preservation
- noise detection
- impulsive noise
- speech enhancement
- floating gate
- flip flops
- computer vision
- gate dielectrics