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Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits.
Masaya Sumita
Shiro Sakiyama
Masayoshi Kinoshita
Yuta Araki
Yuichiro Ikeda
Kohei Fukuoka
Published in:
IEEE J. Solid State Circuits (2005)
Keyphrases
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human body
generation process
high speed
real time
delay insensitive
learning algorithm
computer vision
information systems
digital circuits
variance reduction
logic synthesis