A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.

Shan Jiang Manh Anh Do Kiat Seng Yeo

Published in: VLSI-SoC (Selected Papers) (2006)

Keyphrases

mixed mode
circuit design
analog vlsi
high speed
delay insensitive
cmos technology
vlsi circuits
low voltage
power dissipation
low power
low cost
power consumption
digital circuits
code generation
chip design
data flow
power supply
data driven
end users
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