A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface.
Guodong YinMufeng ZhouYiming ChenWenjun TangZekun YangMingyen LeeXirui DuJinshan YueJiaxin LiuHuazhong YangYongpan LiuXueqing LiPublished in: CoRR (2022)
Keyphrases
- data flow
- gigabit ethernet
- computer networks
- analog to digital converter
- data transfer
- power consumption
- user interface
- parallel processing
- domain specific
- peer to peer
- data transmission
- information processing
- memory requirements
- signal processing
- random access
- digital circuits
- hidden nodes
- wireless sensor networks
- neural network
- dynamic random access memory