Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops.
Jinn-Shyan WangPo-Hui YangDuo ShengPublished in: IEEE J. Solid State Circuits (2000)
Keyphrases
- low power
- cmos technology
- power dissipation
- high speed
- flip flops
- power consumption
- single chip
- low cost
- low power consumption
- vlsi architecture
- nm technology
- logic circuits
- gate array
- digital signal processing
- mixed signal
- vlsi circuits
- power reduction
- wireless transmission
- image processing
- low voltage
- parallel processing
- high frequency
- wireless networks
- pattern recognition
- real time
- ultra low power