Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond.
Noriaki OdaHiroyuki KunishimaTakashi KyounoKazuhiro TakedaTomoaki TanakaToshiyuki TakewakiMasahiro IkedaPublished in: IEICE Trans. Electron. (2006)
Keyphrases
- integrated circuit
- chip design
- circuit design
- single chip
- metal oxide semiconductor
- low cost
- high speed
- building blocks
- power dissipation
- cmos technology
- cmos image sensor
- design process
- computer aided
- analog vlsi
- engineering design
- case study
- evolvable hardware
- design methodology
- low voltage
- printed circuit boards
- image sensor
- low power
- built in self test