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1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating.
Z. Chen
S. H. Kulkarni
V. E. Dorgan
U. Bhattacharya
K. Zhang
Published in:
VLSI Circuits (2016)
Keyphrases
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power consumption
random access memory
neural network
data sets
data fusion
redundant data