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A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication.

Massimo PozzoniSimone ErbaPaolo ViolaMatteo PisatiEmanuele DepaoliDavide SanzogniRiccardo BramaDaniele BaldiMatteo RepossiFrancesco Svelto
Published in: IEEE J. Solid State Circuits (2009)
Keyphrases
  • decision feedback
  • communication systems
  • high speed
  • power consumption
  • physical layer
  • real time
  • learning algorithm
  • multi agent systems
  • computer networks
  • low power
  • communication protocol