8.2 A 12×5 two-dimensional optical I/O array for 600Gb/s chip-to-chip interconnect in 65nm CMOS.
Hiroshi MoritaKoki UchinoEiji OtaniHiizu OhtoriiTakeshi OguraKazunao OnikiShuichi OkaShusaku YanagawaHideyuki SuzukiPublished in: ISSCC (2014)
Keyphrases
- high speed
- focal plane
- analog vlsi
- image sensor
- cmos technology
- random access memory
- power dissipation
- low cost
- nm technology
- low power
- silicon on insulator
- infrared
- programmable logic
- single chip
- ibm power processor
- metal oxide semiconductor
- circuit design
- imaging systems
- three dimensional
- dynamic range
- input output
- chip design
- high density
- multi dimensional
- charge coupled device
- low voltage
- cmos image sensor
- embedded dram
- real time
- ultra low power