A dynamically reconfigurable SIMD processor for a vision chip.
Takashi KomuroShingo KagamiMasatoshi IshikawaPublished in: IEEE J. Solid State Circuits (2004)
Keyphrases
- single chip
- high speed
- highly parallel
- single instruction multiple data
- floating point unit
- parallel processing
- processor core
- parallel architectures
- ibm power processor
- real time
- functional verification
- low cost
- memory subsystem
- massively parallel
- floating point
- vision system
- parallel algorithm
- chip design
- computer vision
- low power
- multithreading
- ibm zenterprise
- parallel processors
- high density
- high end
- image processing
- vlsi implementation
- parallel implementation
- memory bandwidth
- analog vlsi
- random access memory
- smart camera
- processor array
- single processor
- circuit design
- image processing algorithms