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Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation.
Mohammad Moradinezhad Maryan
Seyed Javad Azhari
Mehdi Ayat
Reza Rezaei Siahrood
Published in:
J. Circuits Syst. Comput. (2020)
Keyphrases
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high speed
power dissipation
low power
low error
power consumption
logic circuits
case study
design process
chip design
power reduction
digital signal processing
data model
low cost
efficient implementation
design methodology
user interface
training set
cmos technology
training data
feature selection
real time
database