Layout techniques for FPGA switch blocks.
Herman SchmitVikas ChandraPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2005)
Keyphrases
- high speed
- field programmable gate array
- hardware implementation
- low cost
- real time image processing
- data acquisition
- block size
- systolic array
- low power
- variable size
- layout design
- fpga implementation
- software implementation
- fractal image coding
- signal processing
- dedicated hardware
- functional verification
- pipelined architecture
- low power consumption
- hardware architecture
- cf loadingtexthtml
- real time
- single chip
- hardware design
- dct coefficients
- image processing