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An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration.
Masato Motomura
Yoshiharu Aimoto
Atsufkni Shibayama
Yoshikazu Yabe
Masakazu Yamashina
Published in:
FCCM (1998)
Keyphrases
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embedded dram
random access memory
design considerations
cmos technology
high speed
hardware implementation
low voltage
memory subsystem
low cost
dynamic random access memory
metal oxide semiconductor
real time
signal processing
single chip