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Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking.

Robert WilleGörschwin FeyMarc MessingGerhard AngstLothar LinhardRolf Drechsler
Published in: DSD (2008)
Keyphrases
  • bounded model checking
  • computationally expensive
  • knowledge base
  • model checking
  • database
  • neural network
  • multi agent
  • lightweight
  • temporal logic
  • formal verification