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Performance and Area Trade-Off of 3D-Stacked DRAM Based Chip Multiprocessor with Hybrid Interconnect.
Rakesh Pandey
Aryabartta Sahu
Published in:
IEEE Trans. Emerg. Top. Comput. (2021)
Keyphrases
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trade off
high density
high speed
dynamic random access memory
main memory
memory subsystem
power dissipation
physical design
embedded dram
analog vlsi
database machines
real time
scheduling algorithm
low cost
data structure
cmos technology
low power
low voltage
random access memory
data center