An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS.
Daniel BankmanLita YangBert MoonsMarian VerhelstBoris MurmannPublished in: ISSCC (2018)
Keyphrases
- mixed signal
- cmos technology
- low power
- embedded dram
- parallel processing
- vlsi circuits
- low voltage
- random access memory
- single chip
- power dissipation
- high speed
- power consumption
- clock frequency
- nm technology
- analog to digital converter
- multi channel
- chip design
- low cost
- dynamic random access memory
- silicon on insulator
- memory management
- processor core
- digital circuits
- low power consumption
- digital signal processing
- image sensor
- memory subsystem
- level parallelism
- cmos image sensor
- multithreading
- design considerations
- signal processing
- image processing
- real time