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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

Won-Joo YunHyun-Woo LeeDongsuk ShinShin-Deok KangJi-Yeon YangHyeng-Ouk LeeDong-Uk LeeSujeong SimYoung-Ju KimWon-Jun ChoiKeun-Soo SongSang-Hoon ShinHyang-Hwa ChoiHyung-Wook MoonSeung-Wook KwackJung-Woo LeeYoung-Kyoung ChoiNak-Kyu ParkKwan-Weon KimYoung-Jung ChoiJin-Hong AhnYe Seok Yang
Published in: ISSCC (2008)
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