A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms.
Daniel Mealha CabritaCarlos Raimundo Erig LimaPublished in: J. Circuits Syst. Comput. (2016)
Keyphrases
- logic circuits
- arbitrary topology
- evolutionary algorithm
- gate array
- low power
- low cost
- smooth surfaces
- surface reconstruction
- high speed
- power consumption
- hardware implementation
- shape registration
- field programmable gate array
- power dissipation
- real time
- tunnel diode
- genetic algorithm
- digital signal processing
- signal processing