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Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques.
Chun-Kai Hsu
Li-Ming Denq
Mao-Yin Wang
Jing-Jia Liou
Chih-Tsun Huang
Cheng-Wen Wu
Published in:
ATS (2008)
Keyphrases
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cost reduction
evolutionary algorithm
design process
wireless networks
wireless communication
single chip
ultra low power