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A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs.

Ganesh GoreXifan TangPierre-Emmanuel Gaillardon
Published in: ISPD (2021)
Keyphrases
  • computationally efficient
  • lightweight
  • search algorithm
  • memory efficient
  • rapid prototyping
  • neural network
  • hierarchical clustering
  • parameter tuning
  • web scale
  • parameter free