A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications.
Chao-Tsung HuangMehul TikekarChiraag JuvekarVivienne SzeAnantha P. ChandrakasanPublished in: ISSCC (2013)
Keyphrases
- video decoder
- video codec
- memory subsystem
- video coding
- rate distortion
- video quality
- low power consumption
- video compression
- low bit rate
- high speed
- transform domain
- inter frame
- low cost
- motion compensation
- motion compensated
- low power
- real time
- macroblock
- bit rate
- motion estimation
- bitstream
- power consumption
- frame rate
- image quality
- quality assessment
- spatial domain
- video conferencing
- motion vectors
- single chip
- platform independent
- computer vision