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A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing.

Tony Tae-Hyoung KimJason LiuJohn KeaneChris H. Kim
Published in: IEEE J. Solid State Circuits (2008)
Keyphrases
  • low voltage
  • random access memory
  • design considerations
  • power line
  • knowledge base
  • cmos technology
  • leakage current
  • high speed
  • power management
  • homology generators
  • low power