Login / Signup

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.

Ramin RajaeiBahar AsgariMahmoud TabandehMahdi Fazeli
Published in: Turkish J. Electr. Eng. Comput. Sci. (2017)
Keyphrases
  • cmos technology
  • nano scale
  • low power
  • power consumption
  • low voltage
  • high speed
  • parallel processing
  • real time
  • hidden markov models
  • power dissipation
  • spl times
  • embedded dram