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15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia.

Daeyeon KimYusung KimAyush ShrivastavaGyusung ParkAnandkumar Mahadevan PillaiKunal BannoreTri DoanMuktadir RahmanGwanghyeon BaekClifford OngXiaofei WangZheng GuoEric Karl
Published in: ISSCC (2024)
Keyphrases
  • power consumption
  • neural network
  • case study
  • software architecture
  • power reduction
  • e learning
  • user interface
  • low cost
  • design process
  • computer architecture
  • power management