Design automation tool to generate EDIF and VHDL descriptions of circuit by extraction of FPGA configuration.

Dmitry I. Cheremisinov

Published in: EWDTS (2013)

Keyphrases

design automation
circuit design
hardware description language
hardware implementation
high speed
field programmable gate array
hardware design
computer aided design
generation method
fpga implementation
information extraction
integrated circuit
data sets
low cost
reverse engineering
test generation