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Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic.
Shih-Hung Weng
Yu-Min Kuo
Shih-Chieh Chang
Published in:
ACM Trans. Design Autom. Electr. Syst. (2012)
Keyphrases
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asynchronous circuits
delay insensitive
power reduction
digital circuits
logic circuits
logic synthesis
high speed
power dissipation
pattern recognition
power consumption
computer simulation
efficient implementation
low power
micron cmos