10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.
Jen-Huan TsaiHui-Huan WangYang-Chi YenChang-Ming LaiYen-Ju ChenPo-Chiun HuangPing-Hsuan HsiehHsin ChenChao-Cheng LeePublished in: IEEE J. Solid State Circuits (2015)
Keyphrases
- error correction
- analog to digital converter
- power consumption
- metal oxide semiconductor
- power supply
- cmos technology
- low power
- hd video
- error correcting
- low cost
- error detection
- circuit design
- mixed signal
- nm technology
- data hiding
- cmos image sensor
- barcode
- synthetic aperture radar
- high speed
- channel coding
- single chip
- error control
- watermarking scheme
- silicon on insulator
- wide dynamic range
- sar images
- turbo codes
- bit errors
- ldpc codes
- reed solomon
- image sensor
- spatial domain
- bit rate