Sign in
Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects.
Michihiro Koibuchi
Takafumi Watanabe
Atsushi Minamihata
Masahiro Nakao
Tomoyuki Hiroyasu
Hiroki Matsutani
Hideharu Amano
Published in:
ICNC (2011)
Keyphrases
</>
power consumption
tree structure
high speed
high performance computing
input output
tree nodes
power dissipation
fault tolerance
tree construction
neural network
scientific computing
data acquisition
tree structures
response time
data structure
tree models
power distribution
bayesian networks