A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit.
Prashanth BarlaVinod Kumar JoshiSomashekara BhatPublished in: IEEE Access (2020)
Keyphrases
- low power
- logic circuits
- delay insensitive
- high speed
- power dissipation
- power consumption
- cmos technology
- low cost
- micron cmos
- chip design
- high power
- single chip
- image sensor
- vlsi circuits
- power reduction
- digital signal processing
- wireless transmission
- gate array
- random access memory
- ultra low power
- magnetic field
- low power consumption
- flip flops
- vlsi architecture
- mixed signal
- nm technology
- digital circuits
- low voltage
- asynchronous circuits
- power management
- solid state
- signal processing
- cmos image sensor
- wide dynamic range
- data flow
- image processing