Somashekara Bhat

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 5

Top Topics

Formative Evaluation

Delay Insensitive

Top Venues

Int. J. Sens. Networks

J. Circuits Syst. Comput.

Publications

Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat
Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure. J. Circuits Syst. Comput. 31 (8) (2022)
Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat
A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit. IEEE Access 8 (2020)
Vinod Kumar Joshi, Prashanth Barla, Somashekara Bhat, Brajesh Kumar Kaushik
From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review. IEEE Access 8 (2020)
K. Aneesha Acharya, Somashekara Bhat, M. Kanthi
Accelerometer based quantitative outcome measurement for hand function test. Int. J. Sens. Networks 31 (3) (2019)
K. Aneesha Acharya, Somashekara Bhat, M. Kanthi
Load Cell and FSR-Based Hand-Assistive Device. ICACIE (1) (2019)
C. Sundaresan, C. V. S. Chaitanya, P. R. Venkateswaran, Somashekara Bhat, J. Mohan Kumar
Modified reduced delay BCD adder. BMEI (2011)