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Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect.

Jiwon YoonHyunwoo KimBoogyo SimHyunwook ParkYi-Gyeong KimSujin ParkYoungsu KwonJoungho Kim
Published in: ISOCC (2023)
Keyphrases
  • high bandwidth
  • high speed
  • parallel algorithm
  • high density