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DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects.
Seoyoung Jang
Jaewon Lee
Yujin Choi
Donggeon Kim
Gain Kim
Published in:
ISCAS (2024)
Keyphrases
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high speed
low power
low cost
real time
high density
single chip
vlsi implementation
analog vlsi
multiresolution
denoising
detection algorithm
physical design
power dissipation
focal plane
chip design