Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits.
Ganesh C. PatilShafi QureshiPublished in: ISVLSI (2011)
Keyphrases
- low power
- schottky barrier
- cmos technology
- silicon on insulator
- high speed
- power dissipation
- low power consumption
- signal processor
- delay insensitive
- power consumption
- vlsi circuits
- logic circuits
- low cost
- mixed signal
- energy dissipation
- power reduction
- single chip
- low voltage
- field effect transistors
- cost effective
- vlsi architecture
- digital signal processing
- image sensor
- real time
- wide dynamic range
- ultra low power
- analog vlsi
- power saving
- power management