Parallelized and pipelined hardware implementation of computationally expensive prediction filters.
Luis GraciaCarlos Pérez-VidalPublished in: Concurr. Comput. Pract. Exp. (2009)
Keyphrases
- computationally expensive
- hardware implementation
- parallel architecture
- efficient implementation
- signal processing
- prediction accuracy
- software implementation
- computationally efficient
- image processing algorithms
- dedicated hardware
- hardware architecture
- field programmable gate array
- pipeline architecture
- hardware design
- fpga implementation
- memory management
- image binarization
- general purpose
- machine learning
- fpga technology
- fpga device
- pipelined architecture
- distributed memory
- gabor filters
- message passing
- search space
- pattern recognition