On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits.

Lluís Ribas Jordi Carrabina

Published in: DATE (1998)

Keyphrases

high speed
asynchronous circuits
low level
real time
data driven
model checking
numerical simulations
incremental learning
levels of abstraction
knowledge base
lower level
face verification
simulation models
signature verification
incremental version
functional verification