The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip.
Takashi MidorikawaTakayuki KameiToshihiro HanawaHideharu AmanoPublished in: ASP-DAC (1998)
Keyphrases
- interconnection networks
- multistage
- memory subsystem
- multithreading
- processor core
- memory access
- high speed
- single stage
- data access
- dynamic programming
- low cost
- lot sizing
- stochastic programming
- query processing
- parallel computing
- single chip
- message passing
- fault tolerant
- parallel algorithm
- data management
- database systems