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A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process.
Mohammad Moradinezhad Maryan
Seyed Javad Azhari
Majid Amini Valashani
Published in:
Integr. (2022)
Keyphrases
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low power
circuit design
low cost
power consumption
logic circuits
high speed
low power consumption
cmos technology
digital circuits
single chip
delay insensitive
vlsi circuits
mixed signal
gate array
high power
digital signal processing
vlsi architecture
power dissipation
real time