Circuit-level techniques to control gate leakage for sub-100nm CMOS.
Fatih HamzaogluMircea R. StanPublished in: ISLPED (2002)
Keyphrases
- cmos technology
- low voltage
- leakage current
- low power
- nm technology
- metal oxide semiconductor
- power consumption
- high speed
- silicon on insulator
- low cost
- circuit design
- power dissipation
- parallel processing
- levels of abstraction
- analog vlsi
- image sensor
- vlsi circuits
- power management
- control system
- design considerations
- real time
- control method
- control strategy
- data acquisition
- higher level
- reinforcement learning