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A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC.
Haolin Han
Shubin Liu
Hongzhi Liang
Yi Shen
Jianyu Guo
Ruili Ren
Zhangming Zhu
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2024)
Keyphrases
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power consumption
duty cycle
high speed
computationally expensive
data sets
bit vector
cost effective
bit wise