Login / Signup
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.
Ashesh Rastogi
Wei Chen
Alodeep Sanyal
Sandip Kundu
Published in:
VLSI Design (2007)
Keyphrases
</>
leakage current
low voltage
cmos technology
design considerations
random access memory
power line
power management
low power
power consumption
analog vlsi
delay insensitive
mixed signal
vlsi circuits
electrical properties
high speed