Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
Yinhe HanYu HuXiaowei LiHuawei LiAnshuman ChandraXiaoqing WenPublished in: IEICE Trans. Inf. Syst. (2005)
Keyphrases
- low power
- single chip
- power consumption
- high speed
- low cost
- vlsi architecture
- logic circuits
- low power consumption
- cmos technology
- embedded systems
- digital signal processing
- ultra low power
- mixed signal
- power reduction
- design process
- vlsi circuits
- feature selection
- gate array
- vlsi implementation
- image sensor
- message passing
- image processing