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A hybrid NoC design for cache coherence optimization for chip multiprocessors.
Hui Zhao
Ohyoung Jang
Wei Ding
Yuanrui Zhang
Mahmut T. Kandemir
Mary Jane Irwin
Published in:
DAC (2012)
Keyphrases
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case study
low cost
optimal design
design process
single chip
evolvable hardware
optimization problems
low power consumption
user interface
high speed
high density
hybrid learning
network on chip
packet switched