Off-chip bus power minimization using serialization with cache-based encoding.
Khader MohammadAhsan KabeerTarek M. TahaMuhsen OwaidaMahdi WashhaPublished in: Microelectron. J. (2016)
Keyphrases
- multithreading
- memory subsystem
- high speed
- ibm power processor
- silicon on insulator
- chip design
- power consumption
- concurrency control
- objective function
- processor core
- parallel computing
- memory access
- instruction set
- highly efficient
- data access
- low cost
- single chip
- computational power
- distributed memory
- circuit design
- cache misses
- analog vlsi
- high density
- ibm zenterprise
- functional verification
- real time