Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM.
Tomohiro KorikawaAkio KawabataFujun HeEiji OkiPublished in: IEICE Trans. Commun. (2021)
Keyphrases
- memory subsystem
- dynamic random access memory
- gigabit ethernet
- high density
- memory access
- main memory
- real time
- high speed
- multithreading
- content addressable memory
- embedded dram
- instruction set
- ibm zenterprise
- low cost
- parallel architecture
- processing elements
- packet loss
- memory management
- fiber optic
- management system
- packet switching
- computational power
- processor core
- reconfigurable hardware
- memory hierarchy
- central processor
- processing units
- hardware implementation