A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.
Sabyasachi DasSunil P. KhatriPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2008)
Keyphrases
- management system
- computationally expensive
- data flow
- real time
- information systems
- lightweight
- tree structure
- bit parallel
- multi core processors
- master slave
- parallel architecture
- distributed processing
- parallel computation
- computer architecture
- parallel implementation
- parallel processing
- software architecture
- cost effective
- pattern matching
- data model
- learning algorithm