Towards Test Case Generation for Synthesizable VHDL Programs Using Model Checker.
Tolga AyavTugkan TuglularFevzi BelliPublished in: SSIRI (Companion) (2010)
Keyphrases
- test case generation
- model checker
- test suite
- java programs
- test cases
- hardware description language
- field programmable gate array
- model checking
- software testing
- formal verification
- static analysis
- description language
- hardware implementation
- formal specification
- formal methods
- temporal logic
- object oriented systems
- binary decision diagrams
- search algorithm