Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits.
Sudarshan SrinivasanBharath PhanibhushanaArunkumar VijayakumarSandip KunduPublished in: ACM Great Lakes Symposium on VLSI (2011)
Keyphrases
- low power
- cmos technology
- logic circuits
- power dissipation
- high speed
- power consumption
- mixed signal
- single chip
- low cost
- vlsi circuits
- power reduction
- tunnel diode
- delay insensitive
- low power consumption
- digital signal processing
- vlsi architecture
- ultra low power
- chip design
- circuit design
- gate array
- high power
- wireless transmission
- cmos image sensor
- nm technology
- multi channel
- low voltage
- power saving
- design methodology
- signal processor
- analog to digital converter
- real time