Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation.

Rafael B. Schvittz Leomar Soares Paulo Francisco Butzen

Published in: VLSI-SoC (2019)

Keyphrases

logic circuits
high accuracy
prediction accuracy
low power
digital circuits
database
neural network
computational cost
delay insensitive
classification accuracy
logic programming
error rate
computational efficiency
correlation coefficient
genetic algorithm
feature selection