The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors.
Tadaaki YamauchiLance HammondKunle OlukotunPublished in: ARVLSI (1997)
Keyphrases
- memory subsystem
- embedded dram
- random access memory
- main memory
- instruction set
- dynamic random access memory
- ibm zenterprise
- memory access
- processing elements
- memory hierarchy
- parallel computers
- multithreading
- parallel algorithm
- level parallelism
- signal processor
- cmos technology
- parallel architectures
- single instruction multiple data
- video decoder
- parallel computing
- design considerations
- shared memory
- parallel processing
- input output
- computer architecture
- compute intensive
- signal processing
- query processing
- processor array
- memory bandwidth
- power consumption
- high density
- database systems
- parallel processors
- computing power
- data transfer