A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph.
Jianping WuMing LingYang ZhangChen MeiHuan WangPublished in: ASICON (2013)
Keyphrases
- memory access
- memory subsystem
- multithreading
- memory hierarchy
- memory management
- low cost
- data access
- hardware implementation
- ibm zenterprise
- level parallelism
- instruction set
- cache misses
- main memory
- computational power
- memory bandwidth
- shared memory
- parallel computing
- energy minimization
- energy consumption
- speculative execution
- dynamic random access memory
- vlsi implementation
- high speed
- functional units
- processor core
- reconfigurable hardware
- processing elements
- processing units
- parallel processing
- analog vlsi
- random access memory
- embedded dram
- systolic array
- cache conscious
- energy efficiency
- computer architecture
- computing power
- associative memory
- message passing
- field programmable gate array
- video decoder
- floating point
- query processing
- parallel computers